1. Field of the Invention
The present invention relates to a power-on reset circuit and a method of generating a power-on reset signal. More particularly, the present invention relates to a power-on reset circuit and a method of generating a power-on reset signal tolerant of a variation in an ambient temperature.
2. Discussion of Related Art
A complementary metal oxide semiconductor (CMOS) device typically includes a power-on reset circuit. The power-on reset circuit is a circuit for activating internal circuits such as latch circuits, flip-flops, and so forth, after a power supply voltage is stabilized. A typical power-on reset circuit generates a power-on reset signal, which changes to, for example, a logic ‘high’, when the power supply voltage reaches a predetermined level after a power-up.
The design of a power-on reset circuit for a semiconductor device operating with the low power supply voltages is important.
FIG. 1 is a circuit diagram illustrating a power-on reset circuit. FIG. 2 is a graph showing an output waveform of the power-on reset circuit in FIG. 1 operated at a relatively high temperature and at a relatively low temperature. The power-on reset circuit in FIG. 1 is disclosed in the Korean Patent Laid-Open Publication No. 2004-0031861. Referring to FIG. 1, the power-on reset circuit includes a voltage divider 10, a first amplifier 20 and a second amplifier 30.
The voltage divider 10, comprising resistors R1 and R2, adjusts a level of a power supply voltage at which a power-on reset signal POR is activated. A voltage divided by the voltage divider 10 is amplified and inverted by the first amplifier 20, generating an output voltage AOUT. The output voltage AOUT is amplified and inverted by the second amplifier 30, generating the power-on reset signal POR.
The voltage level at which the power-on reset signal POR is activated may vary with the ambient temperature of the semiconductor device. Referring to FIG. 2, at a higher ambient temperature, a voltage level PORH of power supply voltage at which the power-on reset signal POR is activated is lower than a voltage level PORL at a lower ambient temperature. With the higher ambient temperature, a voltage level of power supply voltage at which the power-on reset signal POR is activated may be higher than a voltage level with the lower ambient temperature.
Therefore, a power-on reset circuit is needed having a substantially stable power supply voltage level at which the power-on reset signal is activated, substantially independent of temperature variation.